Good music.
Small box.
Meet Relay.

1. 01 / POWER IN

   Twelve volts, checked at the door.

   • J1HRO DC-005C-20A jack
   • F4011812L150/24 PTC fuse
   • D401SS34 Schottky
   • D402SMBJ15A TVS

   What it does

   Relay runs from an external regulated 12 V adapter. The supply passes a resettable fuse, then a Schottky diode in series, and a TVS diode clamps spikes on the protected rail. USB-C does not power the board, so 12 V is required even for programming.

   Why this part

   The fuse holds 1.5 A and is rated for 24 V. The Schottky blocks a reversed plug. The TVS clamps at 24.4 V (at 24.6 A), and everything downstream was chosen to survive that: an earlier buck candidate, the TPS62160, tops out at 17 V and was dropped for that reason.

   24.4VTVS clamp voltage (datasheet figure used in the design)

   Still open

   About 0.45 A from 12 V is a rough estimate, and the 12 V / 1 A adapter is a planning allowance, not a measurement. There is no hardware power-fail supervisor yet: dropping the output relay on input loss relies on firmware reading VIN_SENSE.

   Supporting parts 3 groups · labelled on the board+

   • Reservoir capacitors

     C401 100 µF / 25 V electrolytic · C402 10 µF

     Sit on the protected 12 V rail after the diode, a local store of charge for the two buck converters that draw from it.

   • Input-voltage sense

     R401 100 kΩ · R402 15 kΩ · C403 10 nF

     A divider scales the protected 12 V by 0.130 into an ADC pin on the ESP32 (IO1), 3.2 V even at the TVS clamp, so it stays within range. C403 smooths that sense node. Firmware is meant to use it to release the output relay early when the adapter is pulled.

   • Test point

     TP401

     Gives the factory fixture a place to measure the protected 12 V rail.

   Sources: docs/electrical-design.md (Power) · KiCad netlist

2. 02 / CLEAN RAILS

   Nine rails from one 12 V input.

   • U6, U7TPS54202 buck
   • U11TPS65131 ± converter
   • U12, U15TPS7A49 LDO
   • U13TPS7A30 LDO
   • U8, U9TPS7A2033 LDO

   What it does

   Two switching regulators turn 12 V into 3.3 V for the ESP32 and an intermediate 5 V. From that 5 V, the TPS65131 makes roughly ±13.6 V. Linear regulators then clean those up into ±12 V for the op-amps and 5 V for the DAC’s analog side. Two small 3.3 V regulators feed the DAC’s digital side and the clock oscillators separately.

   Why this part

   Switchers are efficient but noisy; the linear regulators after them are there for the sensitive parts. The TPS54202 runs up to 28 V, above the input clamp. The DAC’s three 5 V pins must agree within ±0.1 V, so they share one regulated rail. A pull-down keeps the ± converter off until firmware raises ANALOG_EN, so the analog rails start in a known order.

   ±12VOp-amp rails, designed values +11.96 / −12.1 V

   Still open

   Not yet verified: buck loop response with the chosen ceramics, TPS65131 ripple reaching the LDOs, and the thermal rise of U11 and U15 (the DAC regulator drops about 8.6 V, roughly 0.35 W at 40 mA).

   Supporting parts 9 groups · labelled on the board+

   • Feedback dividers that set each voltage

     R601/R602 100k/22.1k → 3.29 V · R701/R702 100k/13.3k → 5.08 V · R1102/R1103 1M/97.6k → +13.64 V · R1104/R1105 1M/88.7k → −13.68 V · R1201/R1202 90.9k/10k → +11.96 V · R1301/R1302 93.1k/10k → −12.1 V · R1501/R1502 32.4k/10k → 5.02 V

     Each regulator compares a fraction of its own output with an internal reference. The ratio of the two resistors decides the output voltage. The negative converter’s divider runs from its VREF pin instead of ground.

   • Feed-forward capacitors

     C606 56 pF · C706 75 pF · C1104 6.8 pF · C1106 7.5 pF · C1203, C1303, C1503 10 nF

     Each sits across the upper resistor of a feedback divider. Values follow TI’s application circuits; they shape how quickly the regulator reacts. Their effect on this board is unmeasured.

   • Inductors, rectifiers and output capacitors

     L601 10 µH + C604/C605 2 × 22 µF (3.3 V) · L701 15 µH + C704/C705 2 × 22 µF (5 V) · L1101, L1102 4.7 µH + D1101, D1102 B5819W + C1109–C1112 4 × 10 µF

     The switching stages store energy in the inductor each cycle; the capacitors smooth the result. In the ± converter, the B5819W Schottky diodes rectify the boost and inverting outputs.

   • Bootstrap capacitors

     C603, C703 100 nF

     Connected between each buck’s BOOT and switch pins; they power the high-side switch driver.

   • Input and output decoupling

     C601/C602, C701/C702 10 µF + 100 nF · C1101, C1102 4.7 µF · C801/C802, C901/C902 1 µF · C1201/C1204, C1301/C1304, C1501/C1504 10 µF

     Local charge at each regulator’s input and output, keeping current loops short. A2 constrains their distance to the regulator pins.

   • Noise-reduction capacitors

     C1202, C1302, C1502 10 nF

     On each TPS7A49/TPS7A30 NR/SS pin. They filter the regulator’s internal reference and soften its start-up.

   • TPS65131 helpers

     R1101 100 Ω + C1103 100 nF · C1105 220 nF · C1107 10 nF, C1108 4.7 nF

     R1101 and C1103 form a small filter on the controller’s own supply pin. C1105 decouples its reference output. C1107 and C1108 sit on its CP and CN compensation pins, one per output.

   • Start-up control

     R403 100 kΩ · Q1101 AO3401A

     R403 pulls ANALOG_EN (IO12) low, so the ± rails, and with them the op-amp and DAC 5 V rails, stay off until firmware enables them. Q1101 is a P-MOSFET driven by the converter’s BSW pin. It disconnects the boost input so +13.6 V falls to 0 V when disabled instead of following the 5 V rail. (Reverse-polarity protection is D401, not this transistor.)

   • Test points

     TP402–TP406

     For measuring the 3.3 V, 5 V, ±13.6 V and clock rails at the factory.

   Sources: docs/electrical-design.md (Power, sequencing) · KiCad netlist

3. 03 / RECEIVE

   The radio, the buffer and the conductor.

   • U1ESP32-S3-WROOM-1-N16R8
   • J2HRO TYPE-C-31-M-12 USB-C
   • U14ST USBLC6-2SC6 ESD

   What it does

   The module joins Wi-Fi, is meant to receive and decode the stream into a buffer, and sends stereo samples to the DAC over I²S as the bus master (data IO4, bit clock IO5, frame clock IO6). It also runs the board: DAC reset, mute and zero flag, the output relay, the analog rail enable and the clock selector. USB-C connects to the chip’s native USB pins (GPIO19/20) for programming.

   Why this part

   The project asked for the ESP32-S3; the module has an integrated antenna, 16 MB flash and 8 MB octal PSRAM. Two seconds of stereo 44.1 kHz audio in 32-bit containers is 705,600 bytes, so a PSRAM ring buffer is plausible. Native USB means the BOM needs no separate USB-to-serial chip. The candidate receiver project advertises S3 support.

   8MBOctal PSRAM for the audio buffer

   Still open

   There is no receiver firmware yet, and the candidate receiver’s licence only allows non-commercial use. A review found C101/C102 about 17–18 mm from the module’s supply pin; they should move closer. USB attach, the ROM bootloader and ESD immunity are untested.

   Supporting parts 7 groups · labelled on the board+

   • Module supply

     C101 22 µF · C102 100 nF

     Reservoir and high-frequency bypass on the 3.3 V digital rail. Flagged by the A2 review as placed too far from the module.

   • Reset and boot straps

     R101 10 kΩ + C103 1 µF · R102 10 kΩ · R103 10 kΩ

     R101 pulls EN high while C103 delays it, giving the supply time to settle before the chip starts (provisional; a supervisor is still recommended). R102 holds BOOT (GPIO0) high for a normal start; the factory fixture pulls it low to enter download mode. R103 pulls GPIO46 low for download compatibility.

   • BOOT and RESET buttons

     SW101 BOOT (GPIO0) · SW102 RESET (EN) · XUNPU TS-1088-AR02016 4 × 3 mm (C720477)

     Each button switches its line to ground; R102 (BOOT) and R101 with C103 (EN) above are the pull-ups and the EN delay. Hold BOOT and tap RESET to force download mode; normal USB-C flashing doesn’t need them.

   • USB-C identity

     R109, R110 5.1 kΩ

     One pull-down on each CC pin tells the host or cable that Relay is a USB device.

   • USB data path

     R107, R108 22 Ω · U14

     Series resistors on D− and D+ (marked as candidates in the review) and an ESD array that clamps static on the data lines at the connector.

   • USB presence detect

     R111 1 kΩ · R112 100 kΩ · Q101 2N7002 · R113 10 kΩ · C104 100 nF

     VBUS turns on Q101 through R111 (R112 keeps it off otherwise). Q101 pulls a 3.3 V line, held high by R113, low on GPIO14. The ESP32 learns that USB is plugged in without 5 V ever touching one of its pins. C104 bypasses VBUS.

   • Factory access

     TP101–TP106

     Pads for ground, 3.3 V, EN, BOOT and the UART, the recovery path for programming.

   Sources: docs/processor-usb.md · docs/airplay-feasibility.md · reports/kicad-happy-review-2026-10-13.md · KiCad netlist

4. 04 / TIMING

   Two crystals, one beat at a time.

   • Y201SCTF 22.5792 MHz oscillator
   • Y202SCTF 24.576 MHz oscillator
   • U16TI SN74LVC1G3157 selector

   What it does

   Both oscillators run all the time. The selector passes one of them on as the master clock, which drives the DAC directly and the ESP32’s I²S clock input. The ESP32 divides its bit and frame clocks from that same signal, so the whole digital path stays in step. GPIO15 chooses: low for 22.5792 MHz, high for 24.576 MHz.

   Why this part

   22.5792 MHz is 512 × 44.1 kHz; 24.576 MHz is 512 × 48 kHz, so each sample-rate family gets an exact clock. The PCM1794A needs its clock synchronous with the frame clock and has no asynchronous jitter rejection, so the clock quality reaches the output. A1 tied two oscillator outputs together; A2’s break-before-make switch keeps them apart.

   512×Clock / sample-rate ratio in both families

   Still open

   The switch is not glitch-free: firmware must mute, disconnect the relay and reset the DAC before changing clocks, and that firmware does not exist yet. The oscillator maker gives no jitter figure, and none has been measured. Network clock drift still needs correction in software.

   Supporting parts 4 groups · labelled on the board+

   • Default clock choice

     R206 100 kΩ

     Pulls CLK_SEL low, so the 44.1 kHz-family oscillator is selected while the ESP32 is in reset.

   • Series resistors

     R204 10 Ω → DAC · R205 33 Ω → ESP32

     Split the selected clock into two branches and damp its edges, following TI’s layout figure for the DAC side.

   • Clock-supply bypass

     C210, C211, C212 100 nF

     Decouple the shared CLK_3V3 rail; C212 is the selector’s local bypass. The rail comes from its own regulator, U9.

   • Probe point

     TP207

     On the DAC’s clock input, for scoping during bring-up.

   Sources: docs/electrical-design.md (Clock — A2) · firmware/INTEGRATION.md (A2 clock selection) · KiCad netlist

5. 05 / CONVERT

   Numbers become currents.

   • U2TI PCM1794ADBR

   What it does

   The DAC takes 16- or 24-bit I²S samples and produces a pair of opposite-phase output currents per channel. It is set entirely by its pins: four mode pins tied to ground select I²S, stereo and the sharp roll-off filter, so there is no control bus. Of its control pins, the ESP32 drives only reset and soft mute, and reads the zero-data flag.

   Why this part

   The first choice, ESS’s ES9038Q2M, was out of stock at JLCPCB and LCSC. The AK4493S had only 53 in stock and a gated datasheet. The PCM1794A had 1,024 in stock on 12 October 2026, a public datasheet, a 28-pin package with no exposed pad, and a published TI circuit for 2 Vrms output.

   127dBTI typical dynamic range, its reference circuit (not Relay)

   Still open

   TI’s typical −108 dB THD+N misses the original −110 dB goal, so Relay’s target became −105 dB; neither is measured. The chip’s 192 kHz rating is not a validated Relay mode. Its 250 °C reflow limit must be confirmed with the factory profile.

   Supporting parts 6 groups · labelled on the board+

   • Supply decoupling

     C201, C203 100 nF + C202, C204, C205 10 µF (5 V) · C206 100 nF + C207 10 µF (3.3 V)

     Placed at the DAC’s analog and digital supply pins as in TI’s recommended circuit.

   • Common-voltage capacitors

     C208, C209 47 µF tantalum

     One from each VCOM pin to the 5 V VCC1 node, positive side on the 5 V node, as TI shows. They decouple the DAC’s internal common-voltage nodes, which are analog decoupling points rather than signals.

   • Full-scale current

     R202 10 kΩ, 0.1 %

     From IREF to ground. It sets the DAC’s full-scale output current, so its precision feeds straight into the output level.

   • Safe start-up straps

     R201 10 kΩ · R203 10 kΩ

     R201 pulls MUTE high, so the DAC starts soft-muted. R203 holds RST low until firmware has the clocks running.

   • Digital input resistors

     R104, R105, R106 27 Ω

     On data, bit clock and frame clock, at the ESP32 (driving) end, following TI’s layout figure.

   • Test points

     TP201, TP202

     For the DAC’s 5 V and 3.3 V rails.

   Sources: docs/electrical-design.md (DAC change, DAC facts) · reports/jlc-footprint-match-2026-10-15.md · KiCad netlist

6. 06 / ANALOG

   Currents become a line-level voice.

   • U3, U4OPA1612 I/V pairs (L, R)
   • U5OPA1612 difference stages

   What it does

   Each DAC output current goes into an op-amp that converts it to a voltage (an I/V stage). A difference stage then subtracts each channel’s two opposite-phase halves into one line-level signal, removing the part they share, and rolls off content far above the audio band. Four I/V stages and two difference stages fit in three dual op-amps.

   Why this part

   This is TI’s published 2 Vrms output topology for the PCM1794A, with the OPA1612 in place of TI’s NE5534/LT1028. The 825 Ω feedback resistor is the smallest standard value that still reaches 2 Vrms in the worst case: 2.04–2.31 Vrms, 2.17 nominal. Each board is to be trimmed to 2.00 Vrms at test. The ±12 V rails leave about 2 V beyond the swing allowance at the I/V stage’s −8.53 V extreme.

   2.17VrmsNominal full scale before the per-board trim

   Still open

   I/V loop stability is not simulated. The output is DC-coupled: bipolar-zero error could reach roughly ±0.12 V at the RCA, to be measured before deciding on a servo or capacitor. A review calculated −0.26 dB at 20 kHz from the filter alone, beyond the proposed ±0.10 dB flatness target.

   Supporting parts 5 groups · labelled on the board+

   • I/V feedback (sets gain and the first filter pole)

     R301, R302, R321, R322 825 Ω 0.1 % ∥ C301, C302, C321, C322 2.2 nF C0G

     Each resistor converts the DAC’s current into voltage; the capacitor beside it rolls off high frequencies, a pole near 87.7 kHz. The capacitors also affect stability, which is why changes need simulation first.

   • Difference stage (combines the halves, second pole)

     R303, R305, R323, R325 560 Ω · R304, R306, R324, R326 270 Ω (0.1 % thin film) · C303, C304, C323, C324 2.7 nF C0G

     Matched 560 Ω inputs and 270 Ω feedback/ground legs subtract the two halves and scale the result by 270/560. The 2.7 nF capacitors across the 270 Ω legs add a second pole near 218 kHz. Tight tolerance keeps the arms matched so the shared part cancels.

   • Output resistors

     R307, R327 100 Ω

     In series with each channel’s output. The level calculation includes them as a 100 Ω / 10 kΩ divider into the load; behaviour with 0–2 nF of cable is still to be checked.

   • Op-amp rail bypass

     C305/C306, C325/C326, C341/C342 100 nF

     Six 100 nF capacitors on the ±12 V rails at the three op-amps. A2 placed the measured ones about 2 mm from the supply pins; in A1 some were almost 30 mm away.

   • Probe points

     TP203, TP204 · TP205, TP206

     For the ±12 V op-amp rails and each channel’s output before the relay.

   Sources: docs/electrical-design.md (Output stage) · reports/kicad-happy-review-2026-10-13.md · reports/a2-corrections-2026-10-13.md · KiCad netlist

7. 07 / MUTE

   Silent until everything is ready.

   • K1Omron G6K-2F-Y-5V relay
   • Q3012N7002 driver

   What it does

   The relay sits between the analog stage and the RCA jacks. Released, it shorts both outputs to ground; energised, it connects the amplifier outputs. The ESP32 switches it through Q301 (IO11). Start-up is ordered: DAC muted and in reset, rails and clock stable, reset released, silent data running, then relay on, then mute off. Shutdown reverses it.

   Why this part

   Grounding is the default: with no power, the ESP32 in reset, or firmware not driving the pin, the coil is off and the outputs are held quiet. One two-pole relay switches both channels at once from the 5 V rail.

   NC→ GNDRelay rest state: both outputs grounded

   Still open

   Fast release on power loss depends on firmware (VIN_SENSE) because there is no independent hardware fault override yet. Contact behaviour at small signal levels, release time with the coil clamp, and output DC and transients are all unmeasured.

   Supporting parts 3 groups · labelled on the board+

   • Coil driver

     Q301 2N7002 · R341 100 kΩ

     Q301 switches the coil’s low side. R341 pulls its gate low, so the relay stays off while the ESP32 is in reset or its pin floats.

   • Flyback clamp

     D301 1N4148W

     Across the coil, from its switched end back to 5 V. When Q301 turns off, the coil’s stored energy flows through the diode instead of spiking the transistor.

   • Probe point

     TP208

     On the relay control signal.

   Sources: docs/electrical-design.md (Mute and outputs) · firmware/INTEGRATION.md (Mute state machine) · KiCad netlist

8. 08 / OUTPUT

   Two jacks, line level.

   • J3Same Sky RCJ-011 (L, black)
   • J4Same Sky RCJ-011 (R, black)
   • D302, D303PESD5V0S1BA ESD

   What it does

   Right-angle RCA jacks deliver left and right line-level audio to a powered speaker or amplifier input of 10 kΩ or more. The suggested Yamaha HS4 connection uses LINE 1 with RCA-to-mono-TS cables at the full 2 Vrms. Passive speakers need an amplifier.

   Why this part

   RCA line outputs fit powered monitors and amplifiers without extra hardware. Each jack has an ESD clamp at the connector, so static from a cable is caught before it reaches the relay and op-amps.

   2VrmsFull-scale design target into ≥ 10 kΩ

   Still open

   The RCA footprint was corrected on 16 October 2026 after JLC’s preview showed the barrels facing into the board. J4 is now the same black RCJ-011 as J3 (LCSC C4992678), because the red RCJ-012 had no JLC footprint; colour is cosmetic, and the channels are marked L and R on the silkscreen. Clamp distortion at full swing and hot-plug behaviour are unmeasured; the 1 Vrms alternate profile is unimplemented firmware.

   Supporting parts 2 groups · labelled on the board+

   • ESD clamps

     D302, D303 PESD5V0S1BA

     One from each RCA signal to ground, right at the connector. Whether they add distortion at full swing has to be measured, not assumed.

   • Grounded shells

     J3, J4 shell pins

     Both jack shells connect to the board ground.

   Sources: docs/electrical-design.md (Mute and outputs, RCA protection) · docs/speaker-compatibility.md · reports/jlc-footprint-match-2026-10-15.md · KiCad netlist

Values come from the A2 schematic and exported BOM; roles were traced in the KiCad netlist. Figures marked as targets or datasheet typicals are not Relay measurements. No board has been built or measured, and no firmware exists yet.